This application is based on Patent Application No. 2000-020045 filed Jan. 28, 2000 in Japan, the content of which is incorporated hereinto by reference.
1. Field of the Invention
The present invention relates to a method for forming an embedded gate to realize a high-performance transistor, and particularly to a double-gate field-effect transistor that is obtained by forming fine gates, and a method for manufacturing the same.
2. Description of the Related Art
In connection with a progress of transistors toward miniaturization, a short channel effect that the threshold voltage of the transistor varies due to variation in the gate length of the transistor becomes significant. To prevent the short channel effect and increase driving capability of the transistor, it is known that the use of the double gate structure in the transistor (refer to Japanese Patent Application Laid-open No. 62-1270 (1987)) is the most suitable method.
However, up to the present, there has not been known an industrial method for manufacturing the double gate structure practically. Especially, a method for manufacturing the double gate in such a way that a source and a drain are formed so as to fulfill a specified physical relationship to the upper and lower gates for minimizing parasitic capacitance that hampers a high-speed operation thereof is not yet in sight in every way.
The present invention was devised with intent to solve the above-mentioned problem, and the object of the present invention is to provide a double-gate field-effect transistor with aligned upper and lower gates, and an industrial method for manufacturing the same.
The present invention is devised to achieve such objects as mentioned above, and a first invention as included by the present invention has a transistor structure comprising: a first gate embedded in an insulator on a support substrate and being in contact with an insulating layer on the insulator; a source and a drain formed in a semiconductor layer on the insulating layer; and a second gate formed in an embedded insulating layer that is formed on the semiconductor layer, and is characterized in that the first gate and the second gate are opposite to each other through the intermediaries therebetween consisting of the insulating layer, the semiconductor layer, and the embedded insulating layer.
Furthermore, a second invention as included by the present invention is characterized in that wiring of four electrodes that are to be connected to the source, the drain, the first gate, and the second gate, respectively, is formed in the first invention.
Moreover, a third invention as included by the present invention is characterized in that an adjustment hole that reaches as deep as the support substrate is provided in a depressed manner to position the first gate and the second gate to each other in the first invention.
Furthermore, a fourth invention as included by the present invention is characterized by comprising the steps of: forming a semiconductor layer on a first support substrate through the intermediary of an embedded insulating layer; forming an adjustment hole that penetrates the embedded insulating layer and the semiconductor layer in a depressed manner on the first support substrate; providing further an insulating layer on the semiconductor layer and forming a first gate at a predetermined position set apart from the adjustment hole on the insulating layer; forming the insulator on the insulating layer and further gluing a second support substrate onto the insulator; removing the first support substrate and forming a second gate at a predetermined position set apart from the adjustment hole on the embedded insulating layer; and providing a source and a drain on the embedded insulating layer side and forming wiring of electrodes that connects to the source, the drain, the first gate, and the second gate, respectively.
According to the present invention that specifies such configuration as this, a method for manufacturing easily a double-gate filed-effect transistor with aligned upper and lower gates of a fine structure capable of high-speed operation can be provided.
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments thereof taken in conjunction with the accompanying drawings.